Flash memory devices are utilized as non-volatile memory for computing devices such as desktop and laptop computers, personal digital assistants (PDAs), digital cameras, tablet computers and smartphones. Flash memory devices typically utilize one-transistor memory cells, thereby allowing for high memory densities, high reliability, and low power consumption.
A common type of memory cell used by flash memory devices are NOR and NAND memory cells. Electric charges may be placed on or removed from a flash memory cell to configure the cell into a specific memory state. For example, a single level cell (SLC) may be configured to two single-bit binary states (i.e., 0 or 1). Multi-level cells (MLC) may be programmed to two-bit states (i.e., 00, 01, 10, or 11), three-bit states, and so on.
Reading a memory cell is done by assessing the stored charge of a memory cell by reading it with a read reference voltage level. A configured state of the memory cell is determined based on whether the voltage level of the stored charge is higher or lower than the read reference voltage level. For example, in an SLC, an erased state may be inferred if the voltage level of the stored charge is less than the read reference voltage level, while a programmed state may inferred if the voltage level of the stored charge is higher than the read reference voltage level (for MLCs, there may be several reference voltage levels to correspond to transitions between the plurality of memory states for the MLC).
Because the stored charge of a NAND memory cell is an analog phenomenon, its actual value may not be exactly what was intended, and it may even leak away over time; thus NAND memory units may be subject to errors when reading the data stored in the memory (i.e., the stored charge). When such errors occur while reading data from the memory, an error checking and correction (ECC) code process may be used to detect and correct the errors. Some errors may occur that cannot be corrected by the ECC process (e.g., multi-bit errors wherein the number of errors is higher than the threshold of the respective ECC code).
Errors occurring during read operations on NAND memory units may become more frequent with use. This degradation in the reliability of NAND memory is an ongoing problem. This type of problem may become worse as flash memories move increasingly to smaller geometries and to multiple-bits-per-cell structures, which are understood to have less tolerance for variations in the stored charge.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein. An overview of embodiments of the invention is provided below, followed by a more detailed description with reference to the drawings.